A new truncation algorithm of low hardware cost multiplier

نویسندگان

چکیده

Multiplier is one of the most inevitable arithmetic circuit in digital signal design. Multipliers dissipate high power and occupy significant amount die area. In this paper, a low-error architecture design pre-truncated parallel multiplier presented. The coefficients word length has been truncated to reduce size. This truncation scaled down gate count shortened critical paths partial product array. statistical errors designed are calculated for different pre-truncate values compared. implemented using Stratix III, FPGA device. post fitting report presented which shows saving 36.9 % resources usage, reduction 17 propagation time delay.

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ژورنال

عنوان ژورنال: Periodicals of Engineering and Natural Sciences (PEN)

سال: 2021

ISSN: ['2303-4521']

DOI: https://doi.org/10.21533/pen.v10i1.2596